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DSP56F807PB/D Rev. 4.0, 1/2002
DSP56F807
Product Brief
DSP56F807 16-bit Digital Signal Processor
* * * * Up to 40 MIPS at 80 MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 60K x 16-bit words Program Flash 2K x 16-bit words Program RAM 8K x 16-bit words Data Flash 4K x 16-bit words Data RAM 2K x 16-bit words BootFLASH
6 3 4 6 PWM Outputs Current Sense Inputs Fault Inputs PWM Outputs Current Sense Inputs Fault Inputs A/D1 A/D2 A/D1 A/D2 ADCA VREF ADCB VREF2
* * * * * * * * * * *
Up to 64K x 16- bit words each of external program and data memory Two 6 channel PWM Modules Four 4 channel, 12-bit ADCs Two Quadrature Decoders CAN 2.0 B Module Two Serial Communication Interfaces (SCIs) Serial Peripheral Interface (SPI) Up to four General Purpose Quad Timers JTAG/OnCETM port for debugging 14 Dedicated and 18 Shared GPIO lines 160-pin LQFP or 160 MAPBGA Packages
* * * * *
PWMA
RSTO RESET IRQA
EXTBOOT IRQB 6 JTAG/ OnCE Port VPP VCAPC VDD 2 8 VSS 10* Digital Reg VDDA 3 VSSA 3 Analog Reg
PWMB
3 4 4 4 4 4
Low Voltage Supervisor
4
Quadrature Decoder 0 / Quad Timer A Quadrature Decoder 1 / Quad Timer B Quad Timer C
Interrupt Controller
Program Controller and Hardware Looping Unit
Address Generation Unit
Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators
Bit Manipulation Unit
4 2 4 2 2
Program Memory 61440 x 16 Flash 2048 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 8192 x 16 Flash 4096 x 16 SRAM
*
PAB
* *
PDB
* * * *
IPBB CONTROLS 16
PLL
CLKO
Quad Timer D / Alt Func CAN 2.0A/B SCI0 or GPIO SCI1 or GPIO SPI or GPIO Dedicated GPIO
XDB2 CGDB XAB1 XAB2
16-Bit DSP56800 Core
XTAL Clock Gen EXTAL
*
INTERRUPT CONTROLS 16 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0]
2
4 14
ApplicationSpecific Memory & Peripherals
IPBus Bridge (IPBB)
External Bus Interface Unit
External Address Bus Switch External Data Bus Switch Bus Control
A[00:05] 6 10 16 PS Select DS Select WR Enable RD Enable A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 D[00:15]
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. DSP56F807 Block Diagram
(c) Motorola, Inc., 2002. All rights reserved.
DSP56800 Digital Signal Processing Core Features
* * * * * * * * * * * * * * Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface
DSP56F807 Memory Features
* * Harvard architecture permits as many as three simultaneous accesses to program and data memory On-chip memory including a low cost, high volume flash solution -- 60K x 16-bit words of Program Flash -- 2K x 16-bit words of Program RAM -- 8K x 16-bit words of Data Flash -- 4K x 16-bit words of Data RAM -- 2K x 16-bit words of BootFLASH * Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states -- As much as 64K x 16 bits of data memory -- As much as 64K x 16 bits of program memory
DSP56F807 Peripheral Circuit Features
* Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault tolerant design with deadtime insertion, supports both center and edge aligned modes Four 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules are in sync Two Quadrature Decoders each with four inputs or two additional Quad Timers Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins Two Serial Communication Interfaces each with two pins (or four additional GPIO lines) CAN 2.0 B Module with 2-pin port for transmit and receive
* * * * *
2
DSP56F807 Product Brief
MOTOROLA
* * * * * * * *
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines) Computer-Operating Properly (COP) Watchdog timer Two dedicated external interrupt pins 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins External reset input pin for hardware reset External reset output pin for system reset JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
Energy Information
* * * * Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available
DSP56F807 Description
The DSP56F807 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the DSP56F807 is well-suited for many applications. The DSP56F807 includes many peripherals that are especially useful for applications such as: motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, industrial control for power, lighting, automation. The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications.
"Best in Class" Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique C application code independent of component architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the DSP56F807. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/DSP.
MOTOROLA
DSP56F807 Product Brief
3
Table 1. DSP56F807 Chip Documentation
Topic DSP56800 Family Manual DSP56F801/803/805/807 User's Manual DSP56F807 Technical Data Sheet DSP56F807 Product Brief Description Detailed description of the DSP56800 family architecture, and 16-bit DSP core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the DSP56F807, DSP56F803, DSP56F805, and DSP56F807 Electrical and timing specifications, pin descriptions, and package descriptions Summary description and block diagram of the DSP56F807 core, memory, peripherals and interfaces (this document) Order Number DSP56800FM/D
DSP56F801-7UM/D
DSP56F807/D
DSP56F807PB/D
Ordering Information
Consult a Motorola Semiconductor sales office or authorized distributor to order parts.
Table 2. DSP56F807 Ordering Information
Part DSP56F807 DSP56F807 Supply Voltage 3.0 - 3.6V 3.0 - 3.6V Package Type Low Profile Quad Flat Pack (LQFP) Plastic Ball Grid Array (PBGA) Pin Count 160 160 Frequency (MHz) 80 80 Order Number DSP56F807PY80 DSP56F807VF80
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MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2002. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
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